The present invention generally relates to fabrication of semiconductor devices and more particularly to a substrate processing method and fabrication process of a semiconductor device.
In recent semiconductor integrated circuit devices, it is generally practiced to use a multilayer interconnection structure, in which a number of interconnection layers each burying an interconnection pattern in an interlayer insulation film are stacked, for interconnecting large number of device elements formed on a substrate.
With such a multilayer interconnection structure, the technology of damascene process or dual damascene process is used extensively, in which a depression is formed in advance in a low-K dielectric interlayer insulation film in the form of a desired interconnection pattern or desired via-plug pattern, followed by filling the depression with a low-resistance metal layer such as a Cu layer via a barrier metal layer, and further removing excessive metal layer from the surface of the interlayer insulation film by a CMP (chemical mechanical polishing) process.
With such a multilayer interconnection structure, it is essential to use a low-K dielectric film for the interlayer insulation film in combination low-resistance metal layer such as a Cu layer for reducing the signal delay caused by stray capacitance formed between adjacent interconnection patterns and further for reducing the power consumption, in view of increasing effect of the stray capacitance in modern, highly miniaturized semiconductor devices characterized by large integration density.
Thus, a low-K dielectric material, such as an SiOC (carbon-doped silicon oxide film) film, are used for the interlayer insulation film are used with recent, advanced semiconductor integrated circuit devices. It should be noted that conventionally used low-K dielectric material could provide the value of only 2.4-2.5 for the minimum specific dielectric constant.